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[Other resource] sdram

Description: vhdl 编写的sdram controler, 双通道
Platform: | Size: 3575 | Author: chenchungen | Hits:

[Other resource] Verilog&Vhdl混语言对SDRAM的控制源代码

Description: Verilog&Vhdl混语言对SDRAM的控制源代码，提供了很好的例子，顶层文件为sdrm.v！-VerilogVhdl mixed language SDRAM control of the source code, provided a good example of top-level documents sdrm.v!
Platform: | Size: 250084 | Author: 飞扬 | Hits:

[Other Embeded program] DDR SDRAM控制器的VHDL代码已经测试

Description: DDR SDRAM控制器的VHDL代码已经测试
Platform: | Size: 15466 | Author: bbk2000 | Hits:

[Other] sdram32

Description: sram 存储器控制程序很完整，值得认真研究，很有帮组-SRAM memory control program is very complete, worthy of serious study, is to help groups
Platform: | Size: 23552 | Author: 许曲 | Hits:

[Embeded Linux] K4S281632F-TC75

Description: sdram 的详细资料，好好保留，公司内部所有，不得用于商业。-SDRAM detailed information properly retained within the company for all, not for commercial.
Platform: | Size: 106496 | Author: 李芳 | Hits:

[VHDL-FPGA-Verilog] sdram_vhdl_lattice

Description: sdram_vhdl_lattice，程序已经调通过了，欢迎使用，多多交流哈-sdram_vhdl_lattice, procedures have been transferred through the use of welcome, many exchanges Kazakhstan
Platform: | Size: 181248 | Author: 蒋谦 | Hits:

[Parallel Port] mt48lc2m32b2

Description: the verilog model of sdram-mt48lc2m32b2 device.-the verilog model of sdram- mt48lc2m32b2 d evice.
Platform: | Size: 6144 | Author: nightyboy | Hits:

[VHDL-FPGA-Verilog] mt48lc8m16a2

Description: sdram的行为级模拟模块,可以模拟一个sdram,用于仿真对sdram的控制.-sdram behavioral simulation module can simulate a sdram. Simulation for the control of sdram.
Platform: | Size: 6144 | Author: hxwf801 | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM_Controller

Description: DDR RAM控制器的VHDL源码，实现平台是Lattice FPGA，功能验证通过-DDR RAM controller VHDL source code, achieving the platform of Lattice FPGA, functional verification through
Platform: | Size: 677888 | Author: 钟方 | Hits:

[VHDL-FPGA-Verilog] my_fifo_vhdl

Description: XILINX的FPGA实现的双口ram源码，可作为dsp\SDRAM和pci桥接作用，可直接使用，实际工程通过。-XILINX FPGA Implementation of the dual-port ram source, as dsp \ SDRAM and pci bridge, and can be used directly, through practical projects.
Platform: | Size: 19456 | Author: 朱效志 | Hits:

[DSP program] ADC_DAC

Description: This example streams input from a ADC source to a DAC. An analog signal is acquired block-by-block into SDRAM from the ADC (an AD9244 in this example). The frames are then output with a one-frame delay to the DAC (an AD9744 in this example). In this example, no processing is done on the frames. They are passed unaltered.
Platform: | Size: 23552 | Author: gaofeng | Hits:

[VHDL-FPGA-Verilog] SDRAMtest

Description: SDRAM的读写测试，便于大家深入了解SDRAM的工作原理！-SDRAM read and write tests for our in-depth understanding of the working principle of SDRAM!
Platform: | Size: 156672 | Author: 张文 | Hits:

[VHDL-FPGA-Verilog] vga_system

Description: FPGA读写SDRAM的实例，可以当作IPcore来添加，非常有价值的的程序。-FPGA examples SDRAM read and write, can be used as IPCore to add, a very valuable process.
Platform: | Size: 21392384 | Author: 陈泸华 | Hits:

[VHDL-FPGA-Verilog] T4_sdram_control

Description: verilog语言 利用FPGA控制SDRAM，相信很多朋友都需要 快下载吧-control FPGA Verilog language use SDRAM, believe that many of my friends need to download it faster
Platform: | Size: 19456 | Author: 杜菲 | Hits:

[VHDL-FPGA-Verilog] DE2_LCM_SRAM_PIC_DISPLAY

Description: NIOS下，将图片显示到液晶屏上去，基于DE2板子的，全硬件实现，现将图片烧到SDRAM，然后可以直接显示到液晶屏。
Platform: | Size: 1234944 | Author: 刘赛 | Hits:

[VHDL-FPGA-Verilog] t26a_ibis

Description: ddr sdram 的控制代码，采用VHDL语言书写-ddr sdram control code, the use of VHDL language
Platform: | Size: 281600 | Author: zxb | Hits:

[VHDL-FPGA-Verilog] FaultToleranceTechniquesforSRAMBasedFPGAs

Description: 基于FPGA的SDRAM设计，相信大家都会感兴趣！原版的外文书-FPGA-based SDRAM design, I believe we all are interested! Outside the original instrument
Platform: | Size: 6116352 | Author: 邓振淼 | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM_verilog

Description: DDR（双速率）SDRAM控制器参考设计verilog代码，可以直接用的，很好的-DDR (double rate) SDRAM controller reference design Verilog code, can be directly used, very good
Platform: | Size: 752640 | Author: 宋珂 | Hits:

[Software Engineering] SDRAMController

Description: SDRAM Controller 设计详细文档 ，很有参考价值！-SDRAM Controller Design of detailed documentation, a good reference!
Platform: | Size: 446464 | Author: 王一 | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM_controller

Description: DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application note describes a controller design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz, 16-bit data changes at both clock edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.-DDR SDRAM controller VHDL source code, including detailed design documents. The DDR, DCM, and SelectI/O
Platform: | Size: 132096 | Author: xbl | Hits:
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